PWM-controlled Three Level Stacked Structure LLC Resonant Converter And Method Of Controlling Same

The invention discloses a novel control scheme/strategy for the stacked structure LLC resonant converter. The control scheme includes a control signal as a gating signal of the fourth switch, and gating signals of the first, second and third switches that are operably generated according to the gating signal of the fourth switch. The gating signals of the second switch has a same duty ratio as and a phase shift of 180 degrees from the gating signal of the fourth switch. The gate signals of the first and third switches are complementary with the gate signals of the second and fourth switches, respectively. By adopting the control strategy, a three level LLC resonant network input voltage is generated, which includes Vin, Vin/2 and 0

Method for modeling and parameter extraction of LDMOS devices

A method for modeling the performance of a laterally diffused metal oxide semiconductor (LDMOS) device across a wide temperature range is disclosed. The method comprises the steps of positioning the device in an environment chamber operable to create a plurality of environment temperatures; connecting the pins of the device to a measurement system operable to measure at least one device characteristic; operating the environment chamber to set a series of four environment temperatures, acquiring a value of the device characteristic from the measurement system at each temperature, and extracting a temperature parameter set based on the value of the device characteristic at each temperature, then generating a temperature-scaling model for the device

Novel High Frequency Silicon Carbide Static Induction Transistor-Based Test-Bed for the Acquisition of SiC Power Device Reverse Recovery Characteristics

A test system is presented that utilizes a high-frequency Silicon Carbide (SiC) Static Induction Transistor (SIT) in place of the traditional MOSFET to test reverse recovery characteristics for the new class of SiC power diodes. An easily implementable drive circuit is presented that can drive the high-frequency SIT. The SiC SIT is also compared to a commonly used Si MOSFET in the test circuit application

A Review of Current Research Trends in Power-Electronic Innovations in Cyber-Physical Systems.

In this paper, a broad overview of the current research trends in power-electronic innovations in cyber-physical systems (CPSs) is presented. The recent advances in semiconductor device technologies, control architectures, and communication methodologies have enabled researchers to develop integrated smart CPSs that can cater to the emerging requirements of smart grids, renewable energy, electric vehicles, trains, ships, internet of things (IoTs), etc. The topics presented in this paper include novel power-distribution architectures, protection techniques considering large renewable integration in smart grids, wireless charging in electric vehicles, simultaneous power and information transmission, multi-hop network-based coordination, power technologies for renewable energy and smart transformer, CPS reliability, transactive smart railway grid, and real-time simulation of shipboard power systems. It is anticipated that the research trends presented in this paper will provide a timely and useful overview to the power-electronics researchers with broad applications in CPSs.post-print2.019 K

A Modified Neutral-point Voltage Control Strategy for Three-level Inverters Based on Decomposition of Space Vector Diagram

Capacitor voltage imbalance is a significant problem for three-level inverters. Due to the mid-point modulation of these inverter topologies, the neutral point potential moves up or down depending on the neutral point current direction creating imbalanced voltages among the two capacitors. This imbalanced capacitor voltage causes imbalanced voltage stress among the semiconductor devices and causes increase output voltage and current harmonics. This paper introduces a modified voltage balancing strategy using two-level space vector modulation. By decomposing the three-level space vector diagram into two-level space vector diagram and redistributing the dwell times of the two-level zero space vectors, the modified voltage balancing method ensures minimal NP voltage ripple. Compared to the commonly used NP voltage control method (using 3L SVM [9]), the proposed modified NP voltage control method offers a slightly higher neutral-point voltage ripple and output voltage harmonics but, it has much lower switching loss, code size and execution time